Principal Engineer II – Hardware
Sapienza Consulting is recruiting a Principal Engineer II – Hardware, based in the US. The incumbent will be responsible for the design and development of ASIC products for wireless and satellite communication systems.
Responsibilities of the Principal Engineer II – Hardware
- He/she will participate in System On Chip design and verification and should have experience working on a successful ASIC project through the entire product life cycle (requirements, design, verification, and post silicon bring up).
- He/she must exhibit ability to technically lead the verification team and communicate across a global design team and interface with both peers and management effectively.
- Ideal candidate will have an interest in developing in house training for ASIC verification.
- You will be required to explore state of art verification and design trends. SOC is being developed for wireless and satellite communication systems.
- Familiarity with modem systems is a plus.
Profile of the Principal Engineer II – Hardware
- Bachelors or Masters with a minimum of 10 years of work experience in ASIC design and Verification.
The candidate should have familiarity with many of the SoC technologies such as:
- Knowledge of high-speed Interface Standards (PCIE, SATA, USB, Ethernet)
- Architect SOC systems using ARM interconnects (APB, AHB, AXI, CCI)
- DDR technologies including DDR3L, DDR4, LPDDR4
- ARM Cores (M, R, and A series). Hardening of the ARM codes is a plus.
- Develop Timing constraints for SOC with multiple clock domains
- Low Power Design methodology, develop simulations based on CPF
- Familiar with tools such as Clock domain crossing, Code Coverage
- Advanced knowledge of System Verilog and UVM design methodology
- Virtual Prototype of SOC using software or hardware platforms
- You must be eligible to work within the US.
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